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d a t a sh eet preliminary speci?cation file under integrated circuits, ic02 1999 jun 14 integrated circuits tda8960 atsc 8-vsb demodulator and decoder
1999 jun 14 2 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 features general features one-chip advanced television systems committee (atsc)-compliant demodulator and concatenated trellis (viterbi)/reed solomon decoder with de-interleaver and de-randomizer 0.4 m m process 3.3 v device 64-lead qfp64 package boundary scan test output format: 8-bit wide bus. 8-vsb demodulator on-chip digital circuitry for tuner automatic gain control (agc) square root raised cosine filter with 11.5% roll-off factor fully internal carrier recovery loop mostly internal clock recovery and agc loops with programmable loop filters external indication of demodulator lock. adaptive equalizer feed forward including a decision feedback equalizer (dfe) structure range of - 2.3 to +10.5 m s adaptation based on atsc field sync (trained) and/or 8-vsb data (blind) trellis (viterbi) decoder rate 2 3 (rate 1 2 ungerboeck code based). reed solomon decoder (207, 187 an d t = 10) reed solomon code internal convolutional de-interleaving (i = 52; using internal memory) external indication of uncorrectable error; transport error indicator bit in motion picture export group (mpeg) packet header is also set followed by de-randomizer based on atsc standard. i 2 c-bus interface i 2 c-bus interface to initialize and monitor the demodulator and forward error correction (fec) decoder. operation without i 2 c-bus control is possible (default). document references see the atsc url on http://www.atsc.com for the following related documents: atsc digital television standard (document no. a/53, issued 1995 sep 16) guide to the use of the atsc digital television standard (document no. a/54, issued 1995 oct 04). applications digital atsc compliant tv receivers personal computers with digital television capabilities set-top boxes. ordering information type number package name description version tda8960 qfp64 plastic quad ?at package; 64 leads (lead length 1.95 mm); body 14 20 2.8 mm sot319-2
1999 jun 14 3 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 general description the tda8960 is an atsc-compliant demodulator and forward error correction decoder for reception of 8-vsb modulated signals for terrestrial and cable applications: terrestrial: reception of 8-vsb modulated signals via standard 6 mhz vhf/uhf terrestrial tv channels (tv channels 2 to 69 in the united states) cable: reception of 8-vsb modulated signals via standard 6 mhz vhf/uhf cable tv channels. most of the loop components needed to recover the data from the received symbols are internal. the only required external loop components are a low-speed serial d/a converter and a voltage controlled crystal oscillator (vcxo) for the symbol timing recovery and an opamp integrator for the agc. loop parameters of the clock and carrier recovery can be controlled by the i 2 c-bus. a tuner converts the incoming rf frequency to a fixed if frequency centred at 44 mhz. the output of the tuner is filtered, followed by a down conversion in an if block to a low if frequency centred at 1 2 the vsb symbol rate (or a frequency of approximately 5.38 mhz). the low if signal is applied to the a/d converter. to use its full input span, the a/d converter is located within what is typically a fine agc loop which includes a variable gain stage at the output of the if block. however, it is also possible to apply the tda8960 agc control output directly to the tuner. the detector for the tda8960 agc output is located after the a/d converter and determines the peak level of the incoming signals. after gain control, the low if signal is sampled at a nominal rate of twice the vsb symbol frequency, or approximately 21.5 mhz. the carrier recovery is performed completely internally. this function consists of a digital frequency and frequency phase-locked loop (fpll). data shaping is performed with a square root raised cosine (half nyquist) ?lter with roll-off factor of 11.5%. symbol timing recovery is performed mostly within the tda8960, except that a low cost d/a converter and vcxo are required externally to generate the nominal 21.52 mhz clock signal for the a/d converter and tda8960. after carrier recovery, half nyquist filtering and symbol timing recovery, adaptive equalization is performed based on the use of the atsc field sync (trained equalization) and/or the 8-vsb data itself (blind equalization). the adaptive equalizer uses a dfe structure. after trellis decoding, the stream is de-interleaved with a convolutional de-interleaver (interleaving depth 52). the memory for de-interleaving is on-chip. the reed solomon decoder is atsc-compliant with a length of 207 and can correct up to 10 bytes. the decoded stream is de-randomized using a pseudo random bit sequence (prbs). finally the data is passed to a first-in, first-out (fifo) register that prevents the appearance of irregular gaps in the output data. the output of the tda8960 is an atsc-compliant mpeg-2 packet stream together with a clock. furthermore some signal ?ags are provided to indicate the sync bytes and the valid data bytes. uncorrected blocks are also indicated. the 8-bit wide mpeg-2 stream can be applied to an mpeg-2 transport demultiplexer.
1999 jun 14 4 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 quick reference data note 1. this corresponds to 12 training sequences. symbol parameter conditions min. typ. max. unit v ddd digital supply voltage 3.0 3.3 3.6 v i ddd(tot) total digital supply current v ddd = 3.3 v - 300 - ma f clk clock frequency - 21.52 - mhz f sym symbol frequency - 10.76 - msymbols/s il implementation loss --- db a ro half nyquist ?lter roll-off factor - 11.5 - % t acq acquisition time note 1 -- 290 ms t amb ambient temperature - 20 - +70 c p tot total power dissipation - 1.0 - w
1999 jun 14 5 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 block diagram fig.1 block diagram. - symbol timing recovery - sync recovery and pilot removal - adaptive equalization. (1) the digital front-end consists of the following circuits: - fine agc - carrier recovery - half nyquist filter mgr598 handbook, full pagewidth 29 31 to 33 35 to 37 39, 40 22 24 25 15 14 16 13 19 18 20 21 17 64 63 62 61 27 i 2 c-bus interface boundary scan test serial dac interface reset tda8960 fifo de-randomizer reed solomon decoder de-interleaver trellis decoder digital front-end (1) synchro- nization lock detectors dataclk 59 clk data7 to data0 v ssd1 to v ssd8 v ddd1 to v ddd8 error sop datavalid 56 1 to 8, 11, 12 54 53 agcout eqlockindic lockindic adin0 to adin9 trld trcs trstb trsdo rstan a0 tdi tms tck scl sda a1 trst tdo 23, 34, 45, 57, 9, 26, 41, 60 30, 38, 49,55, 10, 28, 42, 58
1999 jun 14 6 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 pinning symbol pin i/o description adin0 1 i data input bit 0 from adc adin1 2 i data input bit 1 from adc adin2 3 i data input bit 2 from adc adin3 4 i data input bit 3 from adc adin4 5 i data input bit 4 from adc adin5 6 i data input bit 5 from adc adin6 7 i data input bit 6 from adc adin7 8 i data input bit 7 from adc v ddd5 9 - digital supply voltage 5 (3.3 v) v ssd5 10 - digital core ground 5 adin8 11 i data input bit 8 from adc adin9 12 i data input bit 9 from adc a0 13 i i 2 c-bus slave address bit 0 scl 14 i i 2 c-bus clock sda 15 i/o i 2 c-bus serial data a1 16 i i 2 c-bus slave address bit 1 tdi 17 i tap controller data input; note 1 tms 18 i tap controller test mode select; note 1 tck 19 i tap controller test clock; note 1 trst 20 i tap controller asynchronous reset; note 1 tdo 21 o tap controller test data output (3-state); note 1 error 22 o transport packet block error signal v ddd1 23 - digital supply voltage 1 (3.3 v) sop 24 o start of transport packet signal datavalid 25 o transport packet data valid signal v ddd6 26 - digital supply voltage 6 (3.3 v) rstan 27 i asynchronous reset v ssd6 28 - digital ground 6 dataclk 29 o transport interface data clock v ssd1 30 - digital ground 1 data7 31 o transport packet data output bit 7 data6 32 o transport packet data output bit 6 data5 33 o transport packet data output bit 5 v ddd2 34 - digital supply voltage 2 (3.3 v) data4 35 o transport packet data output bit 4 data3 36 o transport packet data output bit 3 data2 37 o transport packet data output bit 2 v ssd2 38 - digital ground 2 data1 39 o transport packet data output bit 1 data0 40 o transport packet data output bit 0
1999 jun 14 7 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 note 1. in accordance with the ieee 1149.1 standard; pads tck, tdi, tms and trst are input pads with an internal pull-up transistor and pad tdo is a 3-state output pad. v ddd7 41 - digital supply voltage 7 (3.3 v) v ssd7 42 - digital ground 7 n.c. 43 not connected n.c. 44 not connected v ddd3 45 - digital supply voltage 3 (3.3 v) n.c. 46 not connected n.c. 47 not connected n.c. 48 not connected v ssd3 49 - digital ground 3 n.c. 50 not connected n.c. 51 not connected n.c. 52 not connected lockindic 53 o lock indicator of front-end eqlockindic 54 o lock indicator of equalizer v ssd4 55 - digital ground 4 agcout 56 o agc control signal (3-state) v ddd4 57 - digital supply voltage 4 (3.3 v) v ssd8 58 - digital ground 8 clk 59 i clock v ddd8 60 - digital supply voltage 8 (3.3 v) trsdo 61 o serial data to dac trstb 62 o strobe signal to dac trcs 63 o chip select signal to dac trld 64 o load signal to dac symbol pin i/o description
1999 jun 14 8 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 fig.2 pin configuration. handbook, full pagewidth tda8960 mgr599 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 adin0 adin1 adin2 adin3 adin4 adin5 adin6 adin7 v ddd5 v ssd5 adin8 adin9 a0 tdi tms tck scl sda a1 n.c. n.c. v ssd3 n.c. n.c. n.c. v ddd3 n.c. n.c. v ssd7 v ddd7 data0 data1 v ssd2 data2 data3 data4 v ddd2 data5 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 trld trcs trstb trsdo v ddd8 clk v ssd8 v ddd4 agcout v ssd4 eqlockindic lockindic n.c. trst tdo error v ddd1 sop datavalid v ddd6 rstan v ssd6 dataclk v ssd1 data7 data6
1999 jun 14 9 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 functional description the internal architecture of the tda8960 consists of basically two parts: the front-end containing the agc, carrier recovery, half nyquist filter, symbol timing recovery, sync recovery and adaptive equalization the back-end containing the trellis decoder, de-interleaver, the reed solomon decoder and de-randomizer. agc this block controls an analog gain over a range of up to 20 db. the data from the a/d converter (philips semiconductors tda8763 is recommended) arrives at the vsb demodulator via inputs adin9 to adin0, which is10-bit wide. the format of the incoming samples can be programmed using the i 2 c-bus accessible register 08h. by writing to bit 3 the format can be either twos complement or binary. the absolute value of the input signal is averaged over several samples. the filtered signal is compared to a threshold. the threshold consist of a 4-bit signed value which can be programmed using the i 2 c-bus. the 3-state output signal charges or discharges an off-chip ideal integrator and is used to control the gain controller of the tuner front-end module. the values of the signal are shown in table 1. table 1 agc output the analog low-pass filter or integrator circuit should be designed with an 8 ms time constant. the response of the gain amplifier is linear with respect to the control voltage over the desired range of operation. carrier recovery this circuit recovers the frequency and phase of the pilot carrier. the spectrum during the carrier recovery is displayed in fig.3. pin agcout comment 1 output of the ?lter is smaller than the threshold 0 output of the ?lter is larger than the threshold z output of the ?lter is equal to the threshold by default the carrier is present at 2.69 mhz. during carrier recovery a shift is applied such that the pilot is present at dc. it can happen that the pilot is present at the higher edge of the vsb spectrum. in this event the cr_inv bit in i 2 c-bus register 08h (see table 13) can be set to make sure that after the shift the pilot is at dc. the carrier recovery is capable of tracking a frequency offset of up to 100 khz from the nominal frequency offset within 100 ms. by means of i 2 c-bus read register 03h the current frequency offset in the carrier recovery can be read. this value can be used for fine tuning applications. sync recovery and pilot removal this block performs several functions including pilot removal, segment and field sync removal and rescale agc based on the segment sync. if this block is able to find a data segment sync signal, the external pin lockindic is asserted. the value of this signal can also be read through i 2 c-bus control. adaptive equalization the equalizer consists of a forward filter and a feedback filter section. demodulated symbols from the synchronization and pilot removal block are received every symbol period. the equalizer tries to invert the effects of the channel on the transmitted symbol stream by filtering these symbols. the coefficients of the filters are updated every symbol period using the training sequence. there is also a provision to perform blind equalization. the filtered output is available for the next block, the trellis decoder. fig.3 signal spectrum during carrier recovery. handbook, halfpage mgr600 amplitude (db) frequency (mhz) 5.38 mhz 2.69 5.38 8.07
1999 jun 14 10 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 the equalizer has been designed to correct a maximum pre-echo of 2.32 m s and a maximum post-echo of 10.50 m s. the equalizer uses an overlapping dfe to reduce the effects of co-channel interference. the equalizer has been optimized to have a typical acquisition time of 12 training sequences, which corresponds to approximately 290 ms. the acquisition time has been defined as the time when the output signal-to-noise ratio reaches the threshold of visibility (tov). the atsc defines a tov of 14.9 db for 8-vsb. based on the training signal and the output of the equalizer the mean square error (mse) signal is generated. this 16-bit value is used to control the channel adaptation process and is available though i 2 c-bus control. control the tda8960 contains a complicated finite state machine. this state machine controls the sequence of operations that must be performed when a valid vsb data signal is detected in order for it to be properly decoded into a stream of mpeg-2 transport packets. the following steps have to take place: 1. the external tuner is directed to lock to a specified channel frequency. a vsb signal is present. 2. the tuner agc locks to an acceptable signal gain. 3. the coarse agc of the tda8960 locks to acceptable a/d converter gain. 4. the timing and carrier recovery loops lock to the symbol clock and the carrier frequency. 5. the segment sync pattern is detected. the segment sync lock is acquired. 6. the fine agc locks. 7. the field sync pattern is detected. the mse of the received field sync training sequence is determined. 8. the equalizer uses subsequent training sequences to adapt itself to the channel conditions. 9. the equalizer adapts to the point that the mse of the training sequence is sufficiently small. the trellis decoding, convolutional de-interleaving and reed solomon decoding processes all begin. 10. valid mpeg-2 transport packets are generated. the finite state machine consists of three states. after a reset has been applied, the state machine starts in state 0. s tate 0: channel acquisition in this state either no channel signal is present or a channel signal is being acquired. the agc, timing recovery and carrier recovery loops must first lock onto it. if the segment sync lock is lost, pin lockindic is low, or a hardware reset is applied to the vsb demodulator, the finite state machine returns to state 0. s tate 1: equalizer training the finite state machine remains in state 1 until the mse of the equalized training sequence falls below a certain threshold. it should be noted that in state 1 the back-end is continuously reset to make sure that after the demodulator has locked onto a signal, the trellis decoder and following processing blocks begin at the start of the next complete data field. by means of i 2 c-bus registers 01h and 02h the mse value of the equalizer can be read. this value can be used for applications such as antenna pointing. s tate 2: normal operation normally the state machine would remain in state 2 as long as no synchronization error occurs. if the mse of the equalized training sequence is exceeded for more than 100 ms, the equalizer is reset for one symbol period and the adaptation process starts again. if the demodulator is in this state, the eqlockindic pin signal goes up. the value of this signal can also be read through the i 2 c-bus.
1999 jun 14 11 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 dac interface the tda8960 d/a interface connects to an external off-chip serial d/a converter. it supports four different serial modes. e xternal interface the dac interface consists of pins 61 to 64; see table 2. table 2 dac interface o utput modes table 3 shows which dacs can be used in the different output modes. table 3 dac serial interface modes and dac types the operating mode is programmed by means of the i 2 c-bus interface. bits 4 and 5 of registers 09h control the mode; see table 13. the timing diagrams of the different serial modes are shown in fig.4. modes 0 and 3 do not use the load signal available at pin trld. in mode 3 the output of the timing recovery low-pass filter is inverted to control vcxos which have a negative df/dv. modes 0 and 3 can provide up to 67 ns of the serial data set-up time from the moment the trsdo output has a new data bit until the start of the trstb pulse. in mode 1 the trcs pin is not used. pin function trsdo serial data output trstb strobe signal which can be used by the dac to shift in serial data trcs chip select signal for dac is also used by some dacs to load serially shifted data in the internal parallel register on the positive edge trld load signal used by some dacs to load serially shifted data in the internal parallel latches output mode polarity set-up time (ns) example device 0 +df/dv 67 maxim max531, max538, max539, max504 and max515 texas instruments tlc5615 sipex sp9500 and sp960 linear technology tlc1451 1 +df/dv 45 analog devices ad7943 2 +df/dv 45 analog devices dac8512 3 - df/dv 67 same types as mode 0
1999 jun 14 12 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 fig.4 timing diagrams of the different dac serial interface modes. handbook, full pagewidth mgr601 trcs trstb trsdo d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 handbook, full pagewidth mgr602 trld trstb trsdo d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 handbook, full pagewidth mgr603 trcs trld trstb trsdo d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a. modes 0 and 3 b. mode 1 c. mode 2
1999 jun 14 13 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 transport stream interface the transport stream interface provides an output of 8-bit parallel mpeg-2 transport packets at a data rate of 5.38 mbytes/s. i mplementation the transport interface consists of a fifo, which has two tasks: 1. removal of the field sync segment from the generation of output data 2. increase of the data rate of the de-randomizer from 2.69 to 5.38 mhz. basically the 208 bytes of a field segment (187 data bytes, 20 error correcting bytes and one segment sync byte) are distributed over the remaining 312 data segments. the fifo has a depth of two data segments. as the output data rate is 5.38 mhz we have to distribute 416 bytes, or two field sync data segments over 312 data segments. every mpeg-2 transport packet corresponding to a data segment gets a delay equal to one 5.38 mhz clock cycle. further, every third mpeg-2 transport packet gets an extra delay of one 5.38 mhz transport packet. e xternal interface the transport stream consists of four signals and one data bus as shown in table 4. table 4 transport stream interface f unctional description the timing of the transport stream interface signals is shown in fig.5. name function dataclk output clock datavalid valid demodulator output data or one valid mpeg transport packet data[7 to 0] output data stream (8-bit wide output bus) sop indicates the start of a packet. it goes high at the start of a packet and remains high during the ?rst byte of the packet, the so called sync byte error a transport packet error indicator, which is high for each 188 byte transport packet in which the reed solomon decoder found more errors than it could correct fig.5 timing diagram of the transport interface (normal mode). handbook, full pagewidth mgr604 mpeg-2 sync byte dataclk datavalid data7 to data0 sop error 185.9 ns 185.9 ns 188 bytes/34.9 m s 188 bytes/34.9 m s 77.5 m s 00h 00h sync
1999 jun 14 14 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 the dataclk signal is the 5.38 mhz demodulator output clock. it is derived from the system clock of 21.52 mhz. a few remarks can be made about the dataclk signal: if a reset is applied, dataclk becomes low; it remains low until reset is released and the symbol timing recovery block has detected the synchronization signals after a channel change the dataclk signal stops; it starts again after the system has been locked on to a valid signal if the reed solomon decoder produces an invalid transport packet and the error signal is asserted the dataclk signal continues to change state if the sync recovery block is not able to detect the field sync or data segment sync, dataclk will not change. the datavalid signal indicates valid demodulator output data or one valid mpeg-2 transport packet. it is active high for 188 bytes, or 34.9 m s. the zero bytes to be sent after the 188 valid bytes of the transport packet can be considered to be zeroed parity bytes. sop or start of packet signal is high during the first byte of the packet. the error signal indicates that the transport packet contains uncorrectable output. the error signal becomes high in the following situations: if the reed solomon decoder is unable to correct all errors in a transport packet after a reset has been applied, the error signal is asserted; it remains high until a valid transport packet is produced by the demodulator if the demodulator is out of sync, thus can not detect the field sync and segment sync in the incoming data stream. the error signal can be asserted in the middle of a transport packet. sync byte and transport error indicator the structure of a transport packet header is shown in fig.6. for the vsb demodulator only the first two bytes of the so called transport packet header are important. the first byte in each header of a transport packet is the so called mpeg-2 packet synchronization byte (sync byte). as specified in the mpeg-2 standard, this sync byte must have the same value for all packets. the vsb demodulator ic sets this byte for each outgoing transport packet to 47h. the msb of the second byte in the transport packet is the transport_error_indicator bit. it indicates that the reed solomon decoder was not able to correct all errors and the transport packet has invalid data. fig.6 the structure of a transport packet header. handbook, full pagewidth mgr605 payload (if present) adaptation field (if present) 0 0 msb sync byte transport_error_indicator transport packet header 1st byte 4th byte 1 0 0 0 1 1 1 lsb 188 bytes
1999 jun 14 15 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 boundary scan interface the tda8960 test access port (tap) conforms to the ieee 1149.1 joint test action group (jtag) standard. it is used for board level testing of integrated circuits and for testing the internals of an integrated circuit. the jtag standard defines on-chip test logic, which consists of an instruction register, a group of test data registers including a bypass register and a boundary scan register, four dedicated pins collectively called the test access port (tap) and a tap controller. i nstruction register the instruction register consists of four bits without parity. there are five defined public instructions; see table 5. table 5 public instruction codes notes 1. the bypass instruction provides a minimum length (1-bit) serial path between the tdi and tdo pins when no test operation is required. 2. this instruction can be used to take a sample of the inputs and outputs during normal operation of the component. it can also be used to preload data values into the latched outputs of the boundary scan register. 3. this instructions allows testing off-chip circuitry and board level interconnections. 4. this instruction allows low speed, static testing of the on-chip logic. it can also be used after the chip is mounted on a printed circuit board. 5. this instruction will return the manufacturer id, part number code and version code. for the tda8960 the manufacturer id is b00000010101, the part number code is svsb and the version code is d1. in addition three private instructions are implemented to control different test modes; see table 6. table 6 private instruction codes instruction code selected data register bypass (1) 1111 bypass (initialized state) sample (2) 0001 boundary scan extest (3) 0000 boundary scan intest (4) 0011 boundary scan idcode (5) 0010 identi?cation or bypass instruction code test mode scan_test 1000 test on-chip scan chains bist_test 1001 bist test of de-interleaver ram ram_test 1010 scan test of the on-chip memories char_mode 1011 characterization mode in the characterization mode the ic is scan-testable in the same way as in the scan test mode. however the outputs are not switched to the scan chain outputs. the outputs retain their functionality. it is now possible to scan test pattern through the logic and to verify if the timing constrains at the outputs are met. e xternal interface the tap consists of five pins as shown in table 7.
1999 jun 14 16 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 table 7 tap external interface signal type description tms i test mode select tck i test clock tdi i test data input tdo o test data output trst i test asynchronous reset o peration the tap controller is a finite state machine. it selects a jtag instruction or a data register to store the input based on the tms signal, receives instructions and data on the tdi pin, executes the instruction when triggered by tms, and shifts data out of tdo. tck provides the clock signal for the test logic required by the standard. tck is asynchronous to the system clock. stored devices in the jtag controller must retain their state indefinitely when tck is stopped at logic 0. the signal received at tms is decoded by the tap controller to control test functions. the logic is required to sample tms at the rising edge of tck. serial test instructions and test data are received at tdi. the tdi signal is required to be sampled at the rising edge of tck. when test data is shifted from tdi to tdo, the data must appear without inversion at tdo after a number of rising and falling edges of tck, determined by the length of the instruction or test data register selected. tdo is the serial output for test instructions and data from the tap controller. changes in the state of tdo must occur after the falling edge of tck. this is because devices connected to tdo are required to sample tdo at the rising edge of tck. the tdo driver must be in an inactive state (i.e. tdo line must be flat) except when the scanning of data is in progress. i 2 c-bus interface the i 2 c-bus interface is used to write control information to and read low-speed diagnostic information from the tda8960. the key features of the i 2 c-bus interface are: i 2 c-bus data rate up to 400 kbits/s support for only 7-bit addressing and the possibility of modifying the slave address externally. a typical system using the i 2 c-bus interface is illustrated in fig.7. the tda8960 is connected as a slave to a master through scl and sda. note that the bus has one pull-up resistor for each of the clock and data lines. e xternal interface the i 2 c-bus interface consists of four signals as shown in table 8. table 8 i 2 c-bus external interface the tda8960 has 3.3 v i/o and i 2 c-bus pins. therefore, in a complete system some circuitry might be necessary to allow ics with different supply voltages to communicate and be controlled. this has been described in an application report available from philips semiconductors (application report an97055 , issued 1997 aug 04). signal type description sda i/o i 2 c-bus serial data scl i i 2 c-bus clock a0 i i 2 c-bus slave address bit 0 a1 i i 2 c-bus slave address bit 1 fig.7 typical i 2 c-bus system implementation. handbook, halfpage mgr606 tda8960 i 2 c-bus master v dd r pu scl sda r pu
1999 jun 14 17 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 a ddressing the device addressing the vsb demodulator over the system the i 2 c-bus requires that the 7-bit slave address (a6 to a0) of the device is sent over the bus in accordance with the protocols, together with the r/ w bit equal to logic 1 or 0 to write or read data respectively. the slave address of the device is shown in table 9. bits 0 to 6 are predefined, but bits 0 and 1 can be set using the external pins a0 and a1. table 9 slave address a6 a5 a4 a3 a2 a1 a0 r/ w 00011a1a00= write 1 = read fig.8 a master-transmitter addresses a slave receiver with a 7-bit address (write access). (5) a = acknowledge (sda low) (6) a = not acknowledge (sda high) (7) p = stop condition (8) data transferred (n bytes + acknowledge). (1) from master to slave (2) s = start condition (3) logic 0 (write) (4) from slave to master handbook, full pagewidth mgr607 s a data a (8) data p slave address (1)(2) (1)(3) (4)(5) (1) (4)(5) (4)(5)(6) (1) (1)(7) (1) r/w a/a a write operation is shown in fig.8. after the start condition, the slave address followed by the r/ w bit is transmitted. the receiver, the tda8960, sends an acknowledge and the transmitter starts sending the register values. after each received byte, the tda8960 sends an acknowledge. the transfer stops if the tda8960 does not acknowledge the transfer and/or the master sends a stop condition. if register 08h has to be written to, eight consecutive bytes are written. the first corresponds to register 01h, the second to 02h and so on. the tda8960 will auto-increment the accessed address automatically. up to ten consecutive addresses can be written. in table 11 the default values are given for a number of reserved addresses and reserved bits of certain addresses. these correct default values have to be written in order to prevent unexpected behaviour of the ic. figure 9 shows a read operation. the master sends a start condition followed by the slave address and the r/ w bit is set to logic 1. the slave returns an acknowledge followed by the value of the first address. the master sends another acknowledge and the next value of the address is returned. if the master transmits a stop condition after the acknowledge, the transfer is stopped. up to three consecutive addressed (00h to 03h) can be read.
1999 jun 14 18 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 table 10 i 2 c-bus control register overview (write); note 1 note 1. do not write past address 09h. table 11 i 2 c-bus control registers (default settings after reset) function address d7 d6 d5 d4 d3 d2 d1 d0 operation 00h gnrl_rst initial_rst reserved 01h reserved 02h operation 03h agc_thres reserved 04h reserved 05h reserved 06h reserved 07h carrier recovery 08h ad_fmt cr_inv timing recovery 09h intmod function address d7 d6 d5 d4 d3 d2 d1 d0 operation 00h 00000000 reserved 01h 00000000 reserved 02h 00000100 operation 03h 00000000 reserved 04h 00000010 reserved 05h 10000000 reserved 06h 00000000 reserved 07h 11001010 carrier recovery 08h 00000100 timing recovery 09h 00000000 fig.9 a master-transmitter addresses a slave receiver with a 7-bit address (read access). (5) a = acknowledge (sda low). (6) a = not acknowledge (sda high). (7) p = stop condition. (8) data transferred (n bytes + acknowledge). (1) from master to slave. (2) s = start condition. (3) logic 1 (read). (4) from slave to master. handbook, full pagewidth mgr608 s a data a (8) data p slave address (1)(2) (1)(3) (4)(5) (4) (1)(5) (1)(6) (4) (1)(7) (1) r/w a
1999 jun 14 19 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 table 12 i 2 c-bus diagnostic registers overview (read); note 1 note 1. do not read past address 03h. table 13 i 2 c-bus control registers (write); notes 1 and 2 notes 1. operating modes and control parameters are reset to their initial values. 2. operating modes and control parameters are not affected. function address d7 d6 d5 d4 d3 d2 d1 d0 operation 00h lock_indicator eq_lock_indicator equalizer 01h mse[15 to 8] 02h mse[7 to 0] carrier recovery 03h cr_offset[7 to 0] address function comments bit field name value 00h operation reserved 7 to 2 general reset (note 1) 1 gnrl_reset 0 = disable 1 = enable initial reset (note 2) 0 initial_reset 0 = disable 1 = enable 03h operation reserved 7 to 4 agc threshold value 3 to 0 agc_thres 08h carrier recovery reserved 7 to 4 a/d input format 3 ad_fmt 0 = twos complement 1 = binary inverted spectrum 2 cr_inv 0 = pilot at 8.07 mhz 1 = pilot at 2.69 mhz reserved 1 to 0 09h timing recovery reserved 7 to 6 dac interface mode 5 to 4 int_mod 00 = mode 0 (trld not used) 01 = mode 1 (trcs not used) 10 = mode 2 (trcs and trld are used) 11 = mode 3 (trld not used; negative df/dv reserved 3 to 0
1999 jun 14 20 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 table 14 i 2 c-bus diagnostic registers (read) limiting values in accordance with the absolute maximum rating system (iec 134). notes 1. human body model: c = 100 pf; r = 1.5 k w ; 3 zaps positive and 3 zaps negative. 2. machine model: c = 200 pf; l = 0.5 m h; r = 10 w ; 3 zaps positive and 3 zaps negative. thermal characteristics address function comments bit field name 00h operation reserved 7 to 3 sync recovery lock indicator 2 lock_indicator equalizer lock indicator 1 eq_lock_indicator reserved 0 01h equalizer equalizer mean square error value 15 to 8 mse 02h 7 to 0 mse 03h carrier recovery carrier recovery offset 7 to 0 cr_offset symbol parameter conditions min. typ. max. unit v ddd digital supply voltage 3.0 3.3 3.6 v v i input voltage on any pin with respect to digital ground (v ssd ) - 0.5 - v ddd + 0.5 v i i dc current into any input -- tbf ma i o dc current out of any output -- tbf ma t j junction temperature 0 - 105 c t stg storage temperature --- c t amb ambient temperature - 20 +25 +70 c p tot total power dissipation - 1.0 - w v es electrostatic handling note 1 - 3000 - +3000 v note 2 - 300 - +300 v symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 55 k/w
1999 jun 14 21 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 dc characteristics v ddd = 3.3 v; v ssd = 0 v; t amb =25 c; unless otherwise specified; note 1. notes 1. all supply connections must be made to the same external power supply unit. 2. open-drain output, determined by v ddd via an external pull-up resistor. symbol parameter conditions min. typ. max. unit supply v ddd digital supply voltage 3.0 3.3 3.6 v i ddd digital supply current - 300 - ma inputs v il low-level input voltage -- 0.8 v v ih high-level input voltage 2.0 -- v i li input leakage current -- 1 m a c i input capacitance 8 - 25 pf output v ol low-level output voltage -- 0.4 v v oh high-level output voltage 2.4 -- v i ol low-level output current -- 4ma 3-state output, pin agcout i o(z) high-impedance output current -- 1 m a c o(z) high-impedance output capacitance -- 100 pf i 2 c-bus, pins sda and scl v il low-level input voltage - 0.5 - 0.3v ddd v v ih high-level input voltage 0.7v ddd - v ddd + 0.5 v v ol low-level output voltage 0 - 0.4 v v oh high-level output voltage note 2 -- 3.3 v i ol low-level output current v ol = 0.4 v 3 -- ma i l leakage current v i =v ssd or v ddd -- 10 m a c i input capacitance v i =v ssd -- 8pf
1999 jun 14 22 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 ac characteristics v ddd = 3.3 v; v ssd = 0 v; t amb =25 c; unless otherwise specified. symbol parameter conditions min. typ. max. unit system clock (pin clk) f clk(sys) system clock frequency - 21.52 - mhz t clkh system clock high time - 21.23 - ns t clkl system clock low time note 1 - 21.23 - ns a/d interface (pins adin[9 to 0]) t su(a/d) a/d interface set-up time 5 -- ns t h(a/d) a/d interface hold time 5 -- ns dac interface (pins trsdo, trcs, trld and trstb); see fig.13 t su(d/a) d/a interface set-up time - 40 - ns t h(d/a) d/a interface hold time - 0 - ns transport stream interface (pins data[7 to 0], sop, error and datavalid); see fig.14 t su(d) transport interface data set-up time 5 -- ns t h(d) transport interface data hold time 5 -- ns t dataclkl transport interface dataclk low time 180 -- ns t dataclkh transport interface dataclk high time 180 -- ns t datclkw transport interface dataclk period 371.7 -- ns t dat-val transport interface data to datavalid, error and sop 0 -- ns i 2 c-bus (pins sda and scl); see fig.10 f scl scl clock frequency 0 - 400 khz t buf bus free time between a stop and start condition 1.3 --m s t hd;sta hold time (repeated) start condition; after this period the ?rst clock pulse is generated 0.6 --m s t low low period of the scl clock 1.3 --m s t high high period of the scl clock 0.6 --m s t su;sta set-up time for a repeated start condition 0.6 --m s t su;sto set-up time for stop condition 0.6 --m s t hd;dat data hold time 0 - 0.9 m s t su;dat data set-up time 100 -- ns t sp pulse width of spikes which must be suppressed by the input ?lter tbf - tbf ns t r rise time of both sda and scl signals note 2 20 + 0.1c b - 300 ns
1999 jun 14 23 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 notes 1. the chip clock (clk) comes from a vxco controlled by the external dac. the control loop keeps the clock signal constant at a frequency twice the symbol rate. 2. c b = total capacitance of one bus line in pf. t f fall time of both sda and scl signals note 1 20 + 0.1c b - 300 ns c b capacitive load for each bus line -- 400 pf jtag interface (pins tdo, tdi, tck, tms and trst); see fig.11 t d(tck-tdo) pin tck to tdo valid delay 2 - 10 ns t su(i)(tck) input set-up time to tck 10 -- ns t h(i)(tck) input hold time from tck 2 -- ns reset (pin rstan) t su(po)l power-on set-up time low 23 -- ns symbol parameter conditions min. typ. max. unit
1999 jun 14 24 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... handbook, full pagewidth mbc611 p s sr p t su;sto t sp t hd;sta t su;sta t su;dat t f t high t r t hd;dat t low t hd;sta t buf sda scl fig.10 i 2 c-bus timing diagram.
1999 jun 14 25 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 fig.11 jtag i/o timing. handbook, full pagewidth mgr609 tck tdo t d(tck-tdo) t h(i)(tck) t su(i)(tck) valid fig.12 input timing. t cy(clk) = 46.47 ns. handbook, full pagewidth mgr610 clk adin9 to adin0 t cy(clk) t su(adin) t h(adin) valid fig.13 serial d/a converter interface i/o timing. handbook, full pagewidth mgr611 trstb trsdo t su(d/a) t h(d/a) valid
1999 jun 14 26 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 fig.14 transport interface timing. handbook, full pagewidth mgr612 dataclk data7 to data0 error valid sop t datclkw t dataclkh t dataclkl t su(d) t dat-val t h(d) valid valid
1999 jun 14 27 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 application information fig.15 front-end unit for reception of 8-vsb signals. handbook, full pagewidth mgr597 21.52 mhz mpeg transport stream i 2 c-bus tda8960 i 2 c-bus controller d/a converter vcxo terrestial/cable uhf/vhf a/d converter agc low if tuner
1999 jun 14 28 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 2.90 2.65 0.25 0.50 0.35 0.25 0.14 14.1 13.9 1 18.2 17.6 1.2 0.8 7 0 o o 0.2 0.1 0.2 1.95 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.6 sot319-2 95-02-04 97-08-01 d (1) (1) (1) 20.1 19.9 h d 24.2 23.6 e z 1.2 0.8 d e q e a 1 a l p detail x l (a ) 3 b 19 y c e h a 2 d z d a z e e v m a 1 64 52 51 33 32 20 x pin 1 index b p d h b p v m b w m w m 0 5 10 mm scale qfp64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm sot319-2 a max. 3.20
1999 jun 14 29 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1999 jun 14 30 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, sqfp not suitable suitable hlqfp, hsqfp, hsop, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable
1999 jun 14 31 philips semiconductors preliminary speci?cation atsc 8-vsb demodulator and decoder tda8960 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 1999 66 philips semiconductors C a worldwide company netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero 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philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy printed in the netherlands 545004/01/pp32 date of release: 1999 jun 14 document order number: 9397 750 04248
go to philips semiconductors' home page select & go... start part catalog & datasheets catalog by function discrete semiconductors audio clocks and watches data communications microcontrollers peripherals standard analog video wired communications wireless communications catalog by system automotive consumer multimedia systems communications pc/pc-peripherals cross reference models packages application notes selection guides other technical documentation end of life information datahandbook system relevant links about catalog tree about search about this site subscribe to enews catalog & datasheets search tda8960 tda8960 information as of 2000 - 08 - 20 tda8960; atsc 8 - vsb demodulator and decoder the tda8960 is an atsc - compliant demodulator and forward error correction decoder for reception of 8 - vsb modulated signals for terrestrial and cable applications: l terrestrial: reception of 8 - vsb modulated signals via standard 6 mhz vhf/uhf terrestrial tv channels (tv channels 2 to 69 in the united states) l cable: reception of 8 - vsb modulated signals via standard 6 mhz vhf/uhf cable tv channels. most of the loop components needed to recover the data from the received symbols are internal. the only required external loop components are a low - speed serial d/a converter and a voltage controlled crystal oscillator (vcxo) for the symbol timing recovery and an opamp integrator for the agc. loop parameters of the clock and carrier recovery can be controlled by the i 2 c - bus. a tuner converts the incoming rf frequency to a fixed if frequency centred at 44 mhz. the output of the tuner is filtered, followed by a down conversion in an if block to a low if frequency centred at 1/2 the vsb symbol rate (or a frequency of approximately 5.38 mhz). the low if signal is applied to the a/d converter. to use its full input span, the a/d converter is located within what is typically a fine agc loop which includes a variable gain stage at the output of the if block. however, it is also possible to apply the tda8960 agc control output directly to the tuner. the detector for the tda8960 agc output is located after the a/d converter and determines the peak level of the incoming signals. after gain control, the low if signal is sampled at a nominal rate of twice the vsb symbol frequency, or approximately 21.5 mhz. the carrier recovery is performed completely internally. this function consists of a digital frequency and frequency phase - locked loop (fpll). data shaping is performed with a square root raised cosine (half nyquist) filter with roll - off factor of 11.5%. symbol timing recovery is performed mostly within the tda8960, except that a low cost d/a converter and vcxo are required externally to generate the nominal 21.52 mhz clock signal for the a/d converter and tda8960. ? description ? features ? applications ? datasheet ? products, packages, availability and ordering ? find similar products ? to be kept informed on tda8960, subscribe to enews. subscribe to enews description
after carrier recovery, half nyquist filtering and symbol timing recovery, adaptive equalization is performed based on the use of the atsc field sync (trained equalization) and/or the 8 - vsb data itself (blind equalization). the adaptive equalizer uses a dfe structure. after trellis decoding, the stream is de - interleaved with a convolutional de - interleaver (interleaving depth 52). the memory for de - interleaving is on - chip. the reed solomon decoder is atsc - compliant with a length of 207 and can correct up to 10 bytes. the decoded stream is de - randomized using a pseudo random bit sequence (prbs). finally the data is passed to a first - in, first - out (fifo) register that prevents the appearance of irregular gaps in the output data. the output of the tda8960 is an atsc - compliant mpeg - 2 packet stream together with a clock. furthermore some signal flags are provided to indicate the sync bytes and the valid data bytes. uncorrected blocks are also indicated. the 8 - bit wide mpeg - 2 stream can be applied to an mpeg - 2 transport demultiplexer. general features l one - chip advanced television systems committee (atsc) - compliant demodulator and concatenated trellis (viterbi)/reed solomon decoder with de - interleaver and de - randomizer l 0.4 m process l 3.3 v device l 64 - lead qfp64 package l boundary scan test l output format: 8 - bit wide bus. 8 - vsb demodulator l on - chip digital circuitry for tuner automatic gain control (agc) l square root raised cosine filter with 11.5% roll - off factor l fully internal carrier recovery loop l mostly internal clock recovery and agc loops with programmable loop filters l external indication of demodulator lock. adaptive equalizer l feed forward including a decision feedback equalizer (dfe) structure: l range of - 2.3 to +10.5 &#s l adaptation based on atsc field sync (trained) and/or 8 - vsb data (blind) l trellis (viterbi) decoder l rate 2/3 (rate 1/2 ungerboeck code based). reed solomon decoder features
l (207, 187 and t = 10) reed solomon code l internal convolutional de - interleaving (i = 52; using internal memory) l external indication of uncorrectable error; transport error indicator bit in motion picture export group (mpeg) packet header is also set l followed by de - randomizer based on atsc standard. i 2 c - bus interface l i 2 c - bus interface to initialize and monitor the demodulator and forward error correction (fec) decoder. operation without i 2 c - bus control is possible (default). l digital atsc compliant tv receivers l personal computers with digital television capabilities l set - top boxes. tda8960 links to the similar products page containing an overview of products that are similar in function or related to the part number(s) as listed on this page. the similar products page includes products from the same catalog tree(s) , relevant selection guides and products from the same functional category. applications datasheet type nr. title publication release date datasheet status page count file size (kb) datasheet tda8960 atsc 8-vsb demodulator and decoder 14-jun-99 preliminary specification 32 126 download products, packages, availability and ordering partnumber north american partnumber order code (12nc) marking/packing package device status buy online tda8960h/n1 TDA8960HB 9352 612 22557 standard marking * tray dry pack, bakeable, multiple sot319 samples available find similar products:
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